1. Field of the Invention
The present invention relates to the technical field of timing synchronization and, more particularly, to a horizontal synchronization signal detection system and method.
2. Description of Related Art
Color video burst signal (CVBS) is an NTSC-defined television (TV) transmission signal. FIG. 1 is a schematic view illustrating a typical analog CVBS signal 10. As shown in FIG. 1, the analog CVBS signal 10 includes a front porch 11, a horizontal synchronization (Hsync) pulse 12, a back porch 13, a color video burst 13a, and an active line 14. The Hsync pulse 12 indicates the start portion for each line of the video information. Each Hsync pulse 12 starts with the front porch 11 and ends at the back porch 13. The color video burst 13a is used in various video formats (such as NTSC and PAL) as reference for chrominance signal.
Each line of the analog CVBS signal 10 starts with the falling edge of an Hsync pulse 12 and ends with the falling edge of a next Hsync pulse 12. According to the standard video specification, the level for the front porch 11 and the back porch 13 is referred to as a blanking level (BL), which is 0V. The level (or amplitude) of the Hsync pulse 12 is referred to as a synchronization level (SL), which is a DC level smaller than the BL. The falling and rising edges of the Hsync pulse 12 are defined according to the DC slice level, which is typically 50% of the amplitude of the Hsync pulse.
Currently, various video processing systems and methods have been developed to process the video signal (as shown in FIG. 1) for obtaining video and timing information, so as to drive a display system. For accurately displaying corresponding frames, it requires precisely detecting vertical and horizontal synchronization signals to thereby correctly identify the segmented data frames, and produce and display the line information of each video data frame.
FIG. 2 is a system block diagram of a typical synchronization detector 120. The detector 120 includes a slicer 121, a slice generator 122, a phase detector 123, a phase locked loop (PLL) 124, and a controller 125 to control the aforementioned devices. In general, the slicer 121 detects the rising and falling edges of each Hsync signal of an input video signal 10 based on a DC slice level generated by the slice generator 122. The slice generator 122 uses existing technique to process the input video signal 10 to thereby decide the DC slice level. For example, the DC slice level can be decided according to the DC amplitudes, transformations, and structures of portions of the input video signal or according to the relative amplitude between the Hsync pulse and another level (such as the peak of the BL or active line).
According to the DC slice level determined by the slice generator 122, the slicer 121 can detect the falling edge of the Hsync pulse 12 of the video signal 10 at a point under the determined DC slice level as the level of the input video signal is moved the point. Similarly, the slicer 121 can detect the rising edge of the Hsync pulse 12 of the video signal 10 at a point above the determined DC slice level as the level of the input video signal is moved the point. Namely, when the level (amplitude) of the input video signal 10 is moved to be smaller than the DC slice level, it indicates that the Hsync pulse 12 is detected.
The PLL 124 can generate and output the Hsync pulse 12. The phase detector 123 detects a phase difference between the Hsync pulses extracted from the input video signal 10 by the slicer 121 and outputted by the PLL 124, and thus generates a control signal. The phase difference makes the PLL 124 execute an error correction to adjust the outputted Hsync pulse.
However, such an Hsync detection can affect the level of the input video signal 10 due to the noise interference of the system of FIG. 2, and the level or amplitude of the Hsync pulse 12 is also changed, resulting in that the accuracy of the Hsync detection is decreased. In addition, the signal transmission may cause the deformation or loss of the input video signal, which further makes the Hsync detection more difficult.
US Publication No. 2006/0158553 entitled “Synchronous detector”, which is incorporated by reference herein, has disclosed a horizontal synchronous detector to detect an input video signal and generate a horizontal synchronization level HL for use as a threshold of Hsync signal detection. US Publication No. 2006/0170821 entitled “Digital video processing systems and methods for estimating horizontal sync in digital video signals”, which is incorporated by reference herein, has disclosed a modulus converter to convert an input video signal into a digital input video signal and a digital low pass filter to filter the digital input video signal and generate a threshold THV for use as a level comparison signal for detecting an Hsync signal.
The above schemes use a threshold as a level comparison signal of Hsync detection, but the level of an input video signal is frequently changed due to the noise interference. Therefore, the level comparison schemes in the existing techniques are possibly unable to accurately detect Hsync signal or even unable to detect any Hsync signal, or erroneously take other portions of an input video signal as the Hsync signal.
Therefore, it is desirable to provide an improved horizontal synchronization signal detection system and method to mitigate and/or obviate the aforementioned problems.